Field of Invention
The present invention relates to an integrated circuit (IC) fabrication, and particularly to an overlay mark for checking the alignment accuracy between layers on a wafer, and a measurement method of the overlay mark.
Description of Related Art
As the line width of an integrated circuit process continuously gets narrower, the alignment accuracy between a lower layer and an upper layer becomes more and more important. Therefore, an overlay mark is generally formed on a wafer to check the alignment accuracy between layers.
The existing overlay measurement is an optical image based measurement. The accuracy of the measurement is usually affected by processes including chemical mechanical polishing (CMP), etching, gap fill, film topography, etc. However, it has been difficult to prove the overlay measurement results.